//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
//  Version and Release Control Information:
//
//  File Revision       : 126202
//
//  Release Information : PL401-r0p1-00eac0
//
//------------------------------------------------------------------------------
//  File Purpose        : Structural file that instantiates all the modules
//                        required to implement the build layers module of a
//                        multi layer AXI bus matrix 
//   
//  Key Configuration Details-
//       - Number of build layers (blayers) : 2
//
//  Notes on port naming conventions- 
//
//     All AXI point to point connections can be considered a 
//     MasterInterface - SlaveInterface connection. 
//
//     The AXI ports on the NIC400 AXI BM are named as follows-  
//
//     *_m<n> suffix to denote a MasterInterface (connect to external AXI slave)
//     *_s<n> suffix to denote a SlaveInterface (connect to external AXI master) 
//
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Module Declaration
//------------------------------------------------------------------------------

module nic400_switch2_ml_build_ysyx_rv32
  (

    // SlaveInterface 0 (connects to Master axi_s_0)

    // Write Address Channel
    awuser_s0,
    awid_s0,
    awaddr_s0,
    awlen_s0,
    awsize_s0,
    awburst_s0,
    awlock_s0,
    awcache_s0,
    awprot_s0,
    awvalid_s0,
    awvalid_vect_s0,
    awready_s0,
    aw_qv_s0,
   
    // Write Channel
    wdata_s0,
    wstrb_s0,
    wlast_s0,
    wvalid_s0,
    wready_s0,

    // Write Response Channel
    bid_s0,
    bresp_s0,
    bvalid_s0,
    bready_s0,

    // Read Address Channel
    aruser_s0,
    arid_s0,
    araddr_s0,
    arlen_s0,
    arsize_s0,
    arburst_s0,
    arlock_s0,
    arcache_s0,
    arprot_s0,
    arvalid_s0,
    arvalid_vect_s0,
    arready_s0,
    ar_qv_s0,
   
    // Read Channel
    rid_s0,
    rdata_s0,
    rresp_s0,
    rlast_s0,
    rvalid_s0,
    rready_s0,

    // SlaveInterface 1 (connects to Master axi_s_1)

    // Write Address Channel
    awuser_s1,
    awid_s1,
    awaddr_s1,
    awlen_s1,
    awsize_s1,
    awburst_s1,
    awlock_s1,
    awcache_s1,
    awprot_s1,
    awvalid_s1,
    awvalid_vect_s1,
    awready_s1,
    aw_qv_s1,
   
    // Write Channel
    wdata_s1,
    wstrb_s1,
    wlast_s1,
    wvalid_s1,
    wready_s1,

    // Write Response Channel
    bid_s1,
    bresp_s1,
    bvalid_s1,
    bready_s1,

    // Read Address Channel
    aruser_s1,
    arid_s1,
    araddr_s1,
    arlen_s1,
    arsize_s1,
    arburst_s1,
    arlock_s1,
    arcache_s1,
    arprot_s1,
    arvalid_s1,
    arvalid_vect_s1,
    arready_s1,
    ar_qv_s1,
   
    // Read Channel
    rid_s1,
    rdata_s1,
    rresp_s1,
    rlast_s1,
    rvalid_s1,
    rready_s1,

    // Connects SlaveInterface 0  to MasterInterface 0

    // Write Address Channel
    awuser_0_0,
    awid_0_0,
    awaddr_0_0,
    awlen_0_0,
    awsize_0_0,
    awburst_0_0,
    awlock_0_0,
    awcache_0_0,
    awprot_0_0,
    awvalid_0_0,
    awvalid_vect_0_0,
    awready_0_0,
    aw_qv_0_0,
   
    // Write Channel
    wdata_0_0,
    wstrb_0_0,
    wlast_0_0,
    wvalid_0_0,
    wready_0_0,

    // Write Response Channel
    bid_0_0,
    bresp_0_0,
    bvalid_0_0,
    bready_0_0,

    // Read Address Channel
    aruser_0_0,
    arid_0_0,
    araddr_0_0,
    arlen_0_0,
    arsize_0_0,
    arburst_0_0,
    arlock_0_0,
    arcache_0_0,
    arprot_0_0,
    arvalid_0_0,
    arvalid_vect_0_0,
    arready_0_0,
    ar_qv_0_0,
   
    // Read Channel
    rid_0_0,
    rdata_0_0,
    rresp_0_0,
    rlast_0_0,
    rvalid_0_0,
    rready_0_0,

    // Connects SlaveInterface 0  to MasterInterface 1

    // Write Address Channel
    awuser_0_1,
    awid_0_1,
    awaddr_0_1,
    awlen_0_1,
    awsize_0_1,
    awburst_0_1,
    awlock_0_1,
    awcache_0_1,
    awprot_0_1,
    awvalid_0_1,
    awvalid_vect_0_1,
    awready_0_1,
    aw_qv_0_1,
   
    // Write Channel
    wdata_0_1,
    wstrb_0_1,
    wlast_0_1,
    wvalid_0_1,
    wready_0_1,

    // Write Response Channel
    bid_0_1,
    bresp_0_1,
    bvalid_0_1,
    bready_0_1,

    // Read Address Channel
    aruser_0_1,
    arid_0_1,
    araddr_0_1,
    arlen_0_1,
    arsize_0_1,
    arburst_0_1,
    arlock_0_1,
    arcache_0_1,
    arprot_0_1,
    arvalid_0_1,
    arvalid_vect_0_1,
    arready_0_1,
    ar_qv_0_1,
   
    // Read Channel
    rid_0_1,
    rdata_0_1,
    rresp_0_1,
    rlast_0_1,
    rvalid_0_1,
    rready_0_1,

    // Connects SlaveInterface 0  to MasterInterface 2

    // Write Address Channel
    awuser_0_2,
    awid_0_2,
    awaddr_0_2,
    awlen_0_2,
    awsize_0_2,
    awburst_0_2,
    awlock_0_2,
    awcache_0_2,
    awprot_0_2,
    awvalid_0_2,
    awvalid_vect_0_2,
    awready_0_2,
    aw_qv_0_2,
   
    // Write Channel
    wdata_0_2,
    wstrb_0_2,
    wlast_0_2,
    wvalid_0_2,
    wready_0_2,

    // Write Response Channel
    bid_0_2,
    bresp_0_2,
    bvalid_0_2,
    bready_0_2,

    // Read Address Channel
    aruser_0_2,
    arid_0_2,
    araddr_0_2,
    arlen_0_2,
    arsize_0_2,
    arburst_0_2,
    arlock_0_2,
    arcache_0_2,
    arprot_0_2,
    arvalid_0_2,
    arvalid_vect_0_2,
    arready_0_2,
    ar_qv_0_2,
   
    // Read Channel
    rid_0_2,
    rdata_0_2,
    rresp_0_2,
    rlast_0_2,
    rvalid_0_2,
    rready_0_2,

    // Connects SlaveInterface 0  to MasterInterface 3

    // Write Address Channel
    awuser_0_3,
    awid_0_3,
    awaddr_0_3,
    awlen_0_3,
    awsize_0_3,
    awburst_0_3,
    awlock_0_3,
    awcache_0_3,
    awprot_0_3,
    awvalid_0_3,
    awvalid_vect_0_3,
    awready_0_3,
    aw_qv_0_3,
   
    // Write Channel
    wdata_0_3,
    wstrb_0_3,
    wlast_0_3,
    wvalid_0_3,
    wready_0_3,

    // Write Response Channel
    bid_0_3,
    bresp_0_3,
    bvalid_0_3,
    bready_0_3,

    // Read Address Channel
    aruser_0_3,
    arid_0_3,
    araddr_0_3,
    arlen_0_3,
    arsize_0_3,
    arburst_0_3,
    arlock_0_3,
    arcache_0_3,
    arprot_0_3,
    arvalid_0_3,
    arvalid_vect_0_3,
    arready_0_3,
    ar_qv_0_3,
   
    // Read Channel
    rid_0_3,
    rdata_0_3,
    rresp_0_3,
    rlast_0_3,
    rvalid_0_3,
    rready_0_3,

    // Connects SlaveInterface 0  to MasterInterface 4

    // Write Address Channel
    awuser_0_4,
    awid_0_4,
    awaddr_0_4,
    awlen_0_4,
    awsize_0_4,
    awburst_0_4,
    awlock_0_4,
    awcache_0_4,
    awprot_0_4,
    awvalid_0_4,
    awvalid_vect_0_4,
    awready_0_4,
    aw_qv_0_4,
   
    // Write Channel
    wdata_0_4,
    wstrb_0_4,
    wlast_0_4,
    wvalid_0_4,
    wready_0_4,

    // Write Response Channel
    bid_0_4,
    bresp_0_4,
    bvalid_0_4,
    bready_0_4,

    // Read Address Channel
    aruser_0_4,
    arid_0_4,
    araddr_0_4,
    arlen_0_4,
    arsize_0_4,
    arburst_0_4,
    arlock_0_4,
    arcache_0_4,
    arprot_0_4,
    arvalid_0_4,
    arvalid_vect_0_4,
    arready_0_4,
    ar_qv_0_4,
   
    // Read Channel
    rid_0_4,
    rdata_0_4,
    rresp_0_4,
    rlast_0_4,
    rvalid_0_4,
    rready_0_4,

    // Connects SlaveInterface 0  to MasterInterface 5

    // Write Address Channel
    awuser_0_5,
    awid_0_5,
    awaddr_0_5,
    awlen_0_5,
    awsize_0_5,
    awburst_0_5,
    awlock_0_5,
    awcache_0_5,
    awprot_0_5,
    awvalid_0_5,
    awvalid_vect_0_5,
    awready_0_5,
    aw_qv_0_5,
   
    // Write Channel
    wdata_0_5,
    wstrb_0_5,
    wlast_0_5,
    wvalid_0_5,
    wready_0_5,

    // Write Response Channel
    bid_0_5,
    bresp_0_5,
    bvalid_0_5,
    bready_0_5,

    // Read Address Channel
    aruser_0_5,
    arid_0_5,
    araddr_0_5,
    arlen_0_5,
    arsize_0_5,
    arburst_0_5,
    arlock_0_5,
    arcache_0_5,
    arprot_0_5,
    arvalid_0_5,
    arvalid_vect_0_5,
    arready_0_5,
    ar_qv_0_5,
   
    // Read Channel
    rid_0_5,
    rdata_0_5,
    rresp_0_5,
    rlast_0_5,
    rvalid_0_5,
    rready_0_5,

    // Connects SlaveInterface 0  to MasterInterface 6

    // Write Address Channel
    awuser_0_6,
    awid_0_6,
    awaddr_0_6,
    awlen_0_6,
    awsize_0_6,
    awburst_0_6,
    awlock_0_6,
    awcache_0_6,
    awprot_0_6,
    awvalid_0_6,
    awvalid_vect_0_6,
    awready_0_6,
    aw_qv_0_6,
   
    // Write Channel
    wdata_0_6,
    wstrb_0_6,
    wlast_0_6,
    wvalid_0_6,
    wready_0_6,

    // Write Response Channel
    bid_0_6,
    bresp_0_6,
    bvalid_0_6,
    bready_0_6,

    // Read Address Channel
    aruser_0_6,
    arid_0_6,
    araddr_0_6,
    arlen_0_6,
    arsize_0_6,
    arburst_0_6,
    arlock_0_6,
    arcache_0_6,
    arprot_0_6,
    arvalid_0_6,
    arvalid_vect_0_6,
    arready_0_6,
    ar_qv_0_6,
   
    // Read Channel
    rid_0_6,
    rdata_0_6,
    rresp_0_6,
    rlast_0_6,
    rvalid_0_6,
    rready_0_6,

    // Connects SlaveInterface 0  to MasterInterface 7

    // Write Address Channel
    awuser_0_7,
    awid_0_7,
    awaddr_0_7,
    awlen_0_7,
    awsize_0_7,
    awburst_0_7,
    awlock_0_7,
    awcache_0_7,
    awprot_0_7,
    awvalid_0_7,
    awvalid_vect_0_7,
    awready_0_7,
    aw_qv_0_7,
   
    // Write Channel
    wdata_0_7,
    wstrb_0_7,
    wlast_0_7,
    wvalid_0_7,
    wready_0_7,

    // Write Response Channel
    bid_0_7,
    bresp_0_7,
    bvalid_0_7,
    bready_0_7,

    // Read Address Channel
    aruser_0_7,
    arid_0_7,
    araddr_0_7,
    arlen_0_7,
    arsize_0_7,
    arburst_0_7,
    arlock_0_7,
    arcache_0_7,
    arprot_0_7,
    arvalid_0_7,
    arvalid_vect_0_7,
    arready_0_7,
    ar_qv_0_7,
   
    // Read Channel
    rid_0_7,
    rdata_0_7,
    rresp_0_7,
    rlast_0_7,
    rvalid_0_7,
    rready_0_7,

    // Connects SlaveInterface 0  to MasterInterface 8

    // Write Address Channel
    awuser_0_8,
    awid_0_8,
    awaddr_0_8,
    awlen_0_8,
    awsize_0_8,
    awburst_0_8,
    awlock_0_8,
    awcache_0_8,
    awprot_0_8,
    awvalid_0_8,
    awvalid_vect_0_8,
    awready_0_8,
    aw_qv_0_8,
   
    // Write Channel
    wdata_0_8,
    wstrb_0_8,
    wlast_0_8,
    wvalid_0_8,
    wready_0_8,

    // Write Response Channel
    bid_0_8,
    bresp_0_8,
    bvalid_0_8,
    bready_0_8,

    // Read Address Channel
    aruser_0_8,
    arid_0_8,
    araddr_0_8,
    arlen_0_8,
    arsize_0_8,
    arburst_0_8,
    arlock_0_8,
    arcache_0_8,
    arprot_0_8,
    arvalid_0_8,
    arvalid_vect_0_8,
    arready_0_8,
    ar_qv_0_8,
   
    // Read Channel
    rid_0_8,
    rdata_0_8,
    rresp_0_8,
    rlast_0_8,
    rvalid_0_8,
    rready_0_8,

    // Connects SlaveInterface 1  to MasterInterface 2

    // Write Address Channel
    awuser_1_2,
    awid_1_2,
    awaddr_1_2,
    awlen_1_2,
    awsize_1_2,
    awburst_1_2,
    awlock_1_2,
    awcache_1_2,
    awprot_1_2,
    awvalid_1_2,
    awvalid_vect_1_2,
    awready_1_2,
    aw_qv_1_2,
   
    // Write Channel
    wdata_1_2,
    wstrb_1_2,
    wlast_1_2,
    wvalid_1_2,
    wready_1_2,

    // Write Response Channel
    bid_1_2,
    bresp_1_2,
    bvalid_1_2,
    bready_1_2,

    // Read Address Channel
    aruser_1_2,
    arid_1_2,
    araddr_1_2,
    arlen_1_2,
    arsize_1_2,
    arburst_1_2,
    arlock_1_2,
    arcache_1_2,
    arprot_1_2,
    arvalid_1_2,
    arvalid_vect_1_2,
    arready_1_2,
    ar_qv_1_2,
   
    // Read Channel
    rid_1_2,
    rdata_1_2,
    rresp_1_2,
    rlast_1_2,
    rvalid_1_2,
    rready_1_2,

    // Connects SlaveInterface 1  to MasterInterface 3

    // Write Address Channel
    awuser_1_3,
    awid_1_3,
    awaddr_1_3,
    awlen_1_3,
    awsize_1_3,
    awburst_1_3,
    awlock_1_3,
    awcache_1_3,
    awprot_1_3,
    awvalid_1_3,
    awvalid_vect_1_3,
    awready_1_3,
    aw_qv_1_3,
   
    // Write Channel
    wdata_1_3,
    wstrb_1_3,
    wlast_1_3,
    wvalid_1_3,
    wready_1_3,

    // Write Response Channel
    bid_1_3,
    bresp_1_3,
    bvalid_1_3,
    bready_1_3,

    // Read Address Channel
    aruser_1_3,
    arid_1_3,
    araddr_1_3,
    arlen_1_3,
    arsize_1_3,
    arburst_1_3,
    arlock_1_3,
    arcache_1_3,
    arprot_1_3,
    arvalid_1_3,
    arvalid_vect_1_3,
    arready_1_3,
    ar_qv_1_3,
   
    // Read Channel
    rid_1_3,
    rdata_1_3,
    rresp_1_3,
    rlast_1_3,
    rvalid_1_3,
    rready_1_3,

    // Connects SlaveInterface 1  to MasterInterface 6

    // Write Address Channel
    awuser_1_6,
    awid_1_6,
    awaddr_1_6,
    awlen_1_6,
    awsize_1_6,
    awburst_1_6,
    awlock_1_6,
    awcache_1_6,
    awprot_1_6,
    awvalid_1_6,
    awvalid_vect_1_6,
    awready_1_6,
    aw_qv_1_6,
   
    // Write Channel
    wdata_1_6,
    wstrb_1_6,
    wlast_1_6,
    wvalid_1_6,
    wready_1_6,

    // Write Response Channel
    bid_1_6,
    bresp_1_6,
    bvalid_1_6,
    bready_1_6,

    // Read Address Channel
    aruser_1_6,
    arid_1_6,
    araddr_1_6,
    arlen_1_6,
    arsize_1_6,
    arburst_1_6,
    arlock_1_6,
    arcache_1_6,
    arprot_1_6,
    arvalid_1_6,
    arvalid_vect_1_6,
    arready_1_6,
    ar_qv_1_6,
   
    // Read Channel
    rid_1_6,
    rdata_1_6,
    rresp_1_6,
    rlast_1_6,
    rvalid_1_6,
    rready_1_6,

    // Connects SlaveInterface 1  to MasterInterface 8

    // Write Address Channel
    awuser_1_8,
    awid_1_8,
    awaddr_1_8,
    awlen_1_8,
    awsize_1_8,
    awburst_1_8,
    awlock_1_8,
    awcache_1_8,
    awprot_1_8,
    awvalid_1_8,
    awvalid_vect_1_8,
    awready_1_8,
    aw_qv_1_8,
   
    // Write Channel
    wdata_1_8,
    wstrb_1_8,
    wlast_1_8,
    wvalid_1_8,
    wready_1_8,

    // Write Response Channel
    bid_1_8,
    bresp_1_8,
    bvalid_1_8,
    bready_1_8,

    // Read Address Channel
    aruser_1_8,
    arid_1_8,
    araddr_1_8,
    arlen_1_8,
    arsize_1_8,
    arburst_1_8,
    arlock_1_8,
    arcache_1_8,
    arprot_1_8,
    arvalid_1_8,
    arvalid_vect_1_8,
    arready_1_8,
    ar_qv_1_8,
   
    // Read Channel
    rid_1_8,
    rdata_1_8,
    rresp_1_8,
    rlast_1_8,
    rvalid_1_8,
    rready_1_8,
 
  // Miscelaneous connections
    aclk,
    aresetn
  );


  // SlaveInterface 0 (connects to Master axi_s_0)

  // Write Address Channel
  input [3:0]       awuser_s0;
  input [3:0]       awid_s0;
  input [31:0]      awaddr_s0;
  input [7:0]       awlen_s0;
  input [2:0]       awsize_s0;
  input [1:0]       awburst_s0;
  input             awlock_s0;
  input [3:0]       awcache_s0;
  input [2:0]       awprot_s0;
  input             awvalid_s0;
  input [8:0]            awvalid_vect_s0;
  output            awready_s0;
  input [3:0]       aw_qv_s0;
    
  // Write Channel
  input [31:0]      wdata_s0;
  input [3:0]       wstrb_s0;
  input             wlast_s0;
  input             wvalid_s0;
  output            wready_s0;

  // Write Response Channel
  output [3:0]      bid_s0;
  output [1:0]      bresp_s0;
  output            bvalid_s0;
  input             bready_s0;

  // Read Address Channel
  input [3:0]       aruser_s0;
  input [3:0]       arid_s0;
  input [31:0]      araddr_s0;
  input [7:0]       arlen_s0;
  input [2:0]       arsize_s0;
  input [1:0]       arburst_s0;
  input             arlock_s0;
  input [3:0]       arcache_s0;
  input [2:0]       arprot_s0;
  input             arvalid_s0;
  input [8:0]            arvalid_vect_s0;
  output            arready_s0;
  input [3:0]       ar_qv_s0;
   
  // Read Channel
  output [3:0]      rid_s0;
  output [31:0]     rdata_s0;
  output [1:0]      rresp_s0;
  output            rlast_s0;
  output            rvalid_s0;
  input             rready_s0;

  // SlaveInterface 1 (connects to Master axi_s_1)

  // Write Address Channel
  input [3:0]       awuser_s1;
  input [3:0]       awid_s1;
  input [31:0]      awaddr_s1;
  input [7:0]       awlen_s1;
  input [2:0]       awsize_s1;
  input [1:0]       awburst_s1;
  input             awlock_s1;
  input [3:0]       awcache_s1;
  input [2:0]       awprot_s1;
  input             awvalid_s1;
  input [3:0]            awvalid_vect_s1;
  output            awready_s1;
  input [3:0]       aw_qv_s1;
    
  // Write Channel
  input [31:0]      wdata_s1;
  input [3:0]       wstrb_s1;
  input             wlast_s1;
  input             wvalid_s1;
  output            wready_s1;

  // Write Response Channel
  output [3:0]      bid_s1;
  output [1:0]      bresp_s1;
  output            bvalid_s1;
  input             bready_s1;

  // Read Address Channel
  input [3:0]       aruser_s1;
  input [3:0]       arid_s1;
  input [31:0]      araddr_s1;
  input [7:0]       arlen_s1;
  input [2:0]       arsize_s1;
  input [1:0]       arburst_s1;
  input             arlock_s1;
  input [3:0]       arcache_s1;
  input [2:0]       arprot_s1;
  input             arvalid_s1;
  input [3:0]            arvalid_vect_s1;
  output            arready_s1;
  input [3:0]       ar_qv_s1;
   
  // Read Channel
  output [3:0]      rid_s1;
  output [31:0]     rdata_s1;
  output [1:0]      rresp_s1;
  output            rlast_s1;
  output            rvalid_s1;
  input             rready_s1;

  // Connects SlaveInterface 0  to MasterInterface 0

  // Write Address Channel
  output [3:0]      awuser_0_0;
  output [3:0]      awid_0_0;
  output [31:0]     awaddr_0_0;
  output [7:0]      awlen_0_0;
  output [2:0]      awsize_0_0;
  output [1:0]      awburst_0_0;
  output            awlock_0_0;
  output [3:0]      awcache_0_0;
  output [2:0]      awprot_0_0;
  output            awvalid_0_0;
  output             awvalid_vect_0_0;
  input             awready_0_0;
  output [3:0]      aw_qv_0_0;
   
  // Write Channel
  output  [31:0]    wdata_0_0;
  output  [3:0]     wstrb_0_0;
  output            wlast_0_0;
  output            wvalid_0_0;
  input             wready_0_0;

  // Write Response Channel
  input [3:0]       bid_0_0;
  input [1:0]       bresp_0_0;
  input             bvalid_0_0;
  output            bready_0_0;

  // Read Address Channel
  output  [3:0]     aruser_0_0;
  output  [3:0]     arid_0_0;
  output  [31:0]    araddr_0_0;
  output  [7:0]     arlen_0_0;
  output  [2:0]     arsize_0_0;
  output  [1:0]     arburst_0_0;
  output            arlock_0_0;
  output  [3:0]     arcache_0_0;
  output  [2:0]     arprot_0_0;
  output            arvalid_0_0;
  output            arvalid_vect_0_0;
  input             arready_0_0;
  output  [3:0]     ar_qv_0_0;

  // Read Channel
  input [3:0]       rid_0_0;
  input [31:0]      rdata_0_0;
  input [1:0]       rresp_0_0;
  input             rlast_0_0;
  input             rvalid_0_0;
  output            rready_0_0;

  // Connects SlaveInterface 0  to MasterInterface 1

  // Write Address Channel
  output [3:0]      awuser_0_1;
  output [3:0]      awid_0_1;
  output [31:0]     awaddr_0_1;
  output [7:0]      awlen_0_1;
  output [2:0]      awsize_0_1;
  output [1:0]      awburst_0_1;
  output            awlock_0_1;
  output [3:0]      awcache_0_1;
  output [2:0]      awprot_0_1;
  output            awvalid_0_1;
  output             awvalid_vect_0_1;
  input             awready_0_1;
  output [3:0]      aw_qv_0_1;
   
  // Write Channel
  output  [31:0]    wdata_0_1;
  output  [3:0]     wstrb_0_1;
  output            wlast_0_1;
  output            wvalid_0_1;
  input             wready_0_1;

  // Write Response Channel
  input [3:0]       bid_0_1;
  input [1:0]       bresp_0_1;
  input             bvalid_0_1;
  output            bready_0_1;

  // Read Address Channel
  output  [3:0]     aruser_0_1;
  output  [3:0]     arid_0_1;
  output  [31:0]    araddr_0_1;
  output  [7:0]     arlen_0_1;
  output  [2:0]     arsize_0_1;
  output  [1:0]     arburst_0_1;
  output            arlock_0_1;
  output  [3:0]     arcache_0_1;
  output  [2:0]     arprot_0_1;
  output            arvalid_0_1;
  output            arvalid_vect_0_1;
  input             arready_0_1;
  output  [3:0]     ar_qv_0_1;

  // Read Channel
  input [3:0]       rid_0_1;
  input [31:0]      rdata_0_1;
  input [1:0]       rresp_0_1;
  input             rlast_0_1;
  input             rvalid_0_1;
  output            rready_0_1;

  // Connects SlaveInterface 0  to MasterInterface 2

  // Write Address Channel
  output [3:0]      awuser_0_2;
  output [3:0]      awid_0_2;
  output [31:0]     awaddr_0_2;
  output [7:0]      awlen_0_2;
  output [2:0]      awsize_0_2;
  output [1:0]      awburst_0_2;
  output            awlock_0_2;
  output [3:0]      awcache_0_2;
  output [2:0]      awprot_0_2;
  output            awvalid_0_2;
  output             awvalid_vect_0_2;
  input             awready_0_2;
  output [3:0]      aw_qv_0_2;
   
  // Write Channel
  output  [31:0]    wdata_0_2;
  output  [3:0]     wstrb_0_2;
  output            wlast_0_2;
  output            wvalid_0_2;
  input             wready_0_2;

  // Write Response Channel
  input [3:0]       bid_0_2;
  input [1:0]       bresp_0_2;
  input             bvalid_0_2;
  output            bready_0_2;

  // Read Address Channel
  output  [3:0]     aruser_0_2;
  output  [3:0]     arid_0_2;
  output  [31:0]    araddr_0_2;
  output  [7:0]     arlen_0_2;
  output  [2:0]     arsize_0_2;
  output  [1:0]     arburst_0_2;
  output            arlock_0_2;
  output  [3:0]     arcache_0_2;
  output  [2:0]     arprot_0_2;
  output            arvalid_0_2;
  output            arvalid_vect_0_2;
  input             arready_0_2;
  output  [3:0]     ar_qv_0_2;

  // Read Channel
  input [3:0]       rid_0_2;
  input [31:0]      rdata_0_2;
  input [1:0]       rresp_0_2;
  input             rlast_0_2;
  input             rvalid_0_2;
  output            rready_0_2;

  // Connects SlaveInterface 0  to MasterInterface 3

  // Write Address Channel
  output [3:0]      awuser_0_3;
  output [3:0]      awid_0_3;
  output [31:0]     awaddr_0_3;
  output [7:0]      awlen_0_3;
  output [2:0]      awsize_0_3;
  output [1:0]      awburst_0_3;
  output            awlock_0_3;
  output [3:0]      awcache_0_3;
  output [2:0]      awprot_0_3;
  output            awvalid_0_3;
  output             awvalid_vect_0_3;
  input             awready_0_3;
  output [3:0]      aw_qv_0_3;
   
  // Write Channel
  output  [31:0]    wdata_0_3;
  output  [3:0]     wstrb_0_3;
  output            wlast_0_3;
  output            wvalid_0_3;
  input             wready_0_3;

  // Write Response Channel
  input [3:0]       bid_0_3;
  input [1:0]       bresp_0_3;
  input             bvalid_0_3;
  output            bready_0_3;

  // Read Address Channel
  output  [3:0]     aruser_0_3;
  output  [3:0]     arid_0_3;
  output  [31:0]    araddr_0_3;
  output  [7:0]     arlen_0_3;
  output  [2:0]     arsize_0_3;
  output  [1:0]     arburst_0_3;
  output            arlock_0_3;
  output  [3:0]     arcache_0_3;
  output  [2:0]     arprot_0_3;
  output            arvalid_0_3;
  output            arvalid_vect_0_3;
  input             arready_0_3;
  output  [3:0]     ar_qv_0_3;

  // Read Channel
  input [3:0]       rid_0_3;
  input [31:0]      rdata_0_3;
  input [1:0]       rresp_0_3;
  input             rlast_0_3;
  input             rvalid_0_3;
  output            rready_0_3;

  // Connects SlaveInterface 0  to MasterInterface 4

  // Write Address Channel
  output [3:0]      awuser_0_4;
  output [3:0]      awid_0_4;
  output [31:0]     awaddr_0_4;
  output [7:0]      awlen_0_4;
  output [2:0]      awsize_0_4;
  output [1:0]      awburst_0_4;
  output            awlock_0_4;
  output [3:0]      awcache_0_4;
  output [2:0]      awprot_0_4;
  output            awvalid_0_4;
  output             awvalid_vect_0_4;
  input             awready_0_4;
  output [3:0]      aw_qv_0_4;
   
  // Write Channel
  output  [31:0]    wdata_0_4;
  output  [3:0]     wstrb_0_4;
  output            wlast_0_4;
  output            wvalid_0_4;
  input             wready_0_4;

  // Write Response Channel
  input [3:0]       bid_0_4;
  input [1:0]       bresp_0_4;
  input             bvalid_0_4;
  output            bready_0_4;

  // Read Address Channel
  output  [3:0]     aruser_0_4;
  output  [3:0]     arid_0_4;
  output  [31:0]    araddr_0_4;
  output  [7:0]     arlen_0_4;
  output  [2:0]     arsize_0_4;
  output  [1:0]     arburst_0_4;
  output            arlock_0_4;
  output  [3:0]     arcache_0_4;
  output  [2:0]     arprot_0_4;
  output            arvalid_0_4;
  output            arvalid_vect_0_4;
  input             arready_0_4;
  output  [3:0]     ar_qv_0_4;

  // Read Channel
  input [3:0]       rid_0_4;
  input [31:0]      rdata_0_4;
  input [1:0]       rresp_0_4;
  input             rlast_0_4;
  input             rvalid_0_4;
  output            rready_0_4;

  // Connects SlaveInterface 0  to MasterInterface 5

  // Write Address Channel
  output [3:0]      awuser_0_5;
  output [3:0]      awid_0_5;
  output [31:0]     awaddr_0_5;
  output [7:0]      awlen_0_5;
  output [2:0]      awsize_0_5;
  output [1:0]      awburst_0_5;
  output            awlock_0_5;
  output [3:0]      awcache_0_5;
  output [2:0]      awprot_0_5;
  output            awvalid_0_5;
  output             awvalid_vect_0_5;
  input             awready_0_5;
  output [3:0]      aw_qv_0_5;
   
  // Write Channel
  output  [31:0]    wdata_0_5;
  output  [3:0]     wstrb_0_5;
  output            wlast_0_5;
  output            wvalid_0_5;
  input             wready_0_5;

  // Write Response Channel
  input [3:0]       bid_0_5;
  input [1:0]       bresp_0_5;
  input             bvalid_0_5;
  output            bready_0_5;

  // Read Address Channel
  output  [3:0]     aruser_0_5;
  output  [3:0]     arid_0_5;
  output  [31:0]    araddr_0_5;
  output  [7:0]     arlen_0_5;
  output  [2:0]     arsize_0_5;
  output  [1:0]     arburst_0_5;
  output            arlock_0_5;
  output  [3:0]     arcache_0_5;
  output  [2:0]     arprot_0_5;
  output            arvalid_0_5;
  output            arvalid_vect_0_5;
  input             arready_0_5;
  output  [3:0]     ar_qv_0_5;

  // Read Channel
  input [3:0]       rid_0_5;
  input [31:0]      rdata_0_5;
  input [1:0]       rresp_0_5;
  input             rlast_0_5;
  input             rvalid_0_5;
  output            rready_0_5;

  // Connects SlaveInterface 0  to MasterInterface 6

  // Write Address Channel
  output [3:0]      awuser_0_6;
  output [3:0]      awid_0_6;
  output [31:0]     awaddr_0_6;
  output [7:0]      awlen_0_6;
  output [2:0]      awsize_0_6;
  output [1:0]      awburst_0_6;
  output            awlock_0_6;
  output [3:0]      awcache_0_6;
  output [2:0]      awprot_0_6;
  output            awvalid_0_6;
  output             awvalid_vect_0_6;
  input             awready_0_6;
  output [3:0]      aw_qv_0_6;
   
  // Write Channel
  output  [31:0]    wdata_0_6;
  output  [3:0]     wstrb_0_6;
  output            wlast_0_6;
  output            wvalid_0_6;
  input             wready_0_6;

  // Write Response Channel
  input [3:0]       bid_0_6;
  input [1:0]       bresp_0_6;
  input             bvalid_0_6;
  output            bready_0_6;

  // Read Address Channel
  output  [3:0]     aruser_0_6;
  output  [3:0]     arid_0_6;
  output  [31:0]    araddr_0_6;
  output  [7:0]     arlen_0_6;
  output  [2:0]     arsize_0_6;
  output  [1:0]     arburst_0_6;
  output            arlock_0_6;
  output  [3:0]     arcache_0_6;
  output  [2:0]     arprot_0_6;
  output            arvalid_0_6;
  output            arvalid_vect_0_6;
  input             arready_0_6;
  output  [3:0]     ar_qv_0_6;

  // Read Channel
  input [3:0]       rid_0_6;
  input [31:0]      rdata_0_6;
  input [1:0]       rresp_0_6;
  input             rlast_0_6;
  input             rvalid_0_6;
  output            rready_0_6;

  // Connects SlaveInterface 0  to MasterInterface 7

  // Write Address Channel
  output [3:0]      awuser_0_7;
  output [3:0]      awid_0_7;
  output [31:0]     awaddr_0_7;
  output [7:0]      awlen_0_7;
  output [2:0]      awsize_0_7;
  output [1:0]      awburst_0_7;
  output            awlock_0_7;
  output [3:0]      awcache_0_7;
  output [2:0]      awprot_0_7;
  output            awvalid_0_7;
  output             awvalid_vect_0_7;
  input             awready_0_7;
  output [3:0]      aw_qv_0_7;
   
  // Write Channel
  output  [31:0]    wdata_0_7;
  output  [3:0]     wstrb_0_7;
  output            wlast_0_7;
  output            wvalid_0_7;
  input             wready_0_7;

  // Write Response Channel
  input [3:0]       bid_0_7;
  input [1:0]       bresp_0_7;
  input             bvalid_0_7;
  output            bready_0_7;

  // Read Address Channel
  output  [3:0]     aruser_0_7;
  output  [3:0]     arid_0_7;
  output  [31:0]    araddr_0_7;
  output  [7:0]     arlen_0_7;
  output  [2:0]     arsize_0_7;
  output  [1:0]     arburst_0_7;
  output            arlock_0_7;
  output  [3:0]     arcache_0_7;
  output  [2:0]     arprot_0_7;
  output            arvalid_0_7;
  output            arvalid_vect_0_7;
  input             arready_0_7;
  output  [3:0]     ar_qv_0_7;

  // Read Channel
  input [3:0]       rid_0_7;
  input [31:0]      rdata_0_7;
  input [1:0]       rresp_0_7;
  input             rlast_0_7;
  input             rvalid_0_7;
  output            rready_0_7;

  // Connects SlaveInterface 0  to MasterInterface 8

  // Write Address Channel
  output [3:0]      awuser_0_8;
  output [3:0]      awid_0_8;
  output [31:0]     awaddr_0_8;
  output [7:0]      awlen_0_8;
  output [2:0]      awsize_0_8;
  output [1:0]      awburst_0_8;
  output            awlock_0_8;
  output [3:0]      awcache_0_8;
  output [2:0]      awprot_0_8;
  output            awvalid_0_8;
  output             awvalid_vect_0_8;
  input             awready_0_8;
  output [3:0]      aw_qv_0_8;
   
  // Write Channel
  output  [31:0]    wdata_0_8;
  output  [3:0]     wstrb_0_8;
  output            wlast_0_8;
  output            wvalid_0_8;
  input             wready_0_8;

  // Write Response Channel
  input [3:0]       bid_0_8;
  input [1:0]       bresp_0_8;
  input             bvalid_0_8;
  output            bready_0_8;

  // Read Address Channel
  output  [3:0]     aruser_0_8;
  output  [3:0]     arid_0_8;
  output  [31:0]    araddr_0_8;
  output  [7:0]     arlen_0_8;
  output  [2:0]     arsize_0_8;
  output  [1:0]     arburst_0_8;
  output            arlock_0_8;
  output  [3:0]     arcache_0_8;
  output  [2:0]     arprot_0_8;
  output            arvalid_0_8;
  output            arvalid_vect_0_8;
  input             arready_0_8;
  output  [3:0]     ar_qv_0_8;

  // Read Channel
  input [3:0]       rid_0_8;
  input [31:0]      rdata_0_8;
  input [1:0]       rresp_0_8;
  input             rlast_0_8;
  input             rvalid_0_8;
  output            rready_0_8;

  // Connects SlaveInterface 1  to MasterInterface 2

  // Write Address Channel
  output [3:0]      awuser_1_2;
  output [3:0]      awid_1_2;
  output [31:0]     awaddr_1_2;
  output [7:0]      awlen_1_2;
  output [2:0]      awsize_1_2;
  output [1:0]      awburst_1_2;
  output            awlock_1_2;
  output [3:0]      awcache_1_2;
  output [2:0]      awprot_1_2;
  output            awvalid_1_2;
  output             awvalid_vect_1_2;
  input             awready_1_2;
  output [3:0]      aw_qv_1_2;
   
  // Write Channel
  output  [31:0]    wdata_1_2;
  output  [3:0]     wstrb_1_2;
  output            wlast_1_2;
  output            wvalid_1_2;
  input             wready_1_2;

  // Write Response Channel
  input [3:0]       bid_1_2;
  input [1:0]       bresp_1_2;
  input             bvalid_1_2;
  output            bready_1_2;

  // Read Address Channel
  output  [3:0]     aruser_1_2;
  output  [3:0]     arid_1_2;
  output  [31:0]    araddr_1_2;
  output  [7:0]     arlen_1_2;
  output  [2:0]     arsize_1_2;
  output  [1:0]     arburst_1_2;
  output            arlock_1_2;
  output  [3:0]     arcache_1_2;
  output  [2:0]     arprot_1_2;
  output            arvalid_1_2;
  output            arvalid_vect_1_2;
  input             arready_1_2;
  output  [3:0]     ar_qv_1_2;

  // Read Channel
  input [3:0]       rid_1_2;
  input [31:0]      rdata_1_2;
  input [1:0]       rresp_1_2;
  input             rlast_1_2;
  input             rvalid_1_2;
  output            rready_1_2;

  // Connects SlaveInterface 1  to MasterInterface 3

  // Write Address Channel
  output [3:0]      awuser_1_3;
  output [3:0]      awid_1_3;
  output [31:0]     awaddr_1_3;
  output [7:0]      awlen_1_3;
  output [2:0]      awsize_1_3;
  output [1:0]      awburst_1_3;
  output            awlock_1_3;
  output [3:0]      awcache_1_3;
  output [2:0]      awprot_1_3;
  output            awvalid_1_3;
  output             awvalid_vect_1_3;
  input             awready_1_3;
  output [3:0]      aw_qv_1_3;
   
  // Write Channel
  output  [31:0]    wdata_1_3;
  output  [3:0]     wstrb_1_3;
  output            wlast_1_3;
  output            wvalid_1_3;
  input             wready_1_3;

  // Write Response Channel
  input [3:0]       bid_1_3;
  input [1:0]       bresp_1_3;
  input             bvalid_1_3;
  output            bready_1_3;

  // Read Address Channel
  output  [3:0]     aruser_1_3;
  output  [3:0]     arid_1_3;
  output  [31:0]    araddr_1_3;
  output  [7:0]     arlen_1_3;
  output  [2:0]     arsize_1_3;
  output  [1:0]     arburst_1_3;
  output            arlock_1_3;
  output  [3:0]     arcache_1_3;
  output  [2:0]     arprot_1_3;
  output            arvalid_1_3;
  output            arvalid_vect_1_3;
  input             arready_1_3;
  output  [3:0]     ar_qv_1_3;

  // Read Channel
  input [3:0]       rid_1_3;
  input [31:0]      rdata_1_3;
  input [1:0]       rresp_1_3;
  input             rlast_1_3;
  input             rvalid_1_3;
  output            rready_1_3;

  // Connects SlaveInterface 1  to MasterInterface 6

  // Write Address Channel
  output [3:0]      awuser_1_6;
  output [3:0]      awid_1_6;
  output [31:0]     awaddr_1_6;
  output [7:0]      awlen_1_6;
  output [2:0]      awsize_1_6;
  output [1:0]      awburst_1_6;
  output            awlock_1_6;
  output [3:0]      awcache_1_6;
  output [2:0]      awprot_1_6;
  output            awvalid_1_6;
  output             awvalid_vect_1_6;
  input             awready_1_6;
  output [3:0]      aw_qv_1_6;
   
  // Write Channel
  output  [31:0]    wdata_1_6;
  output  [3:0]     wstrb_1_6;
  output            wlast_1_6;
  output            wvalid_1_6;
  input             wready_1_6;

  // Write Response Channel
  input [3:0]       bid_1_6;
  input [1:0]       bresp_1_6;
  input             bvalid_1_6;
  output            bready_1_6;

  // Read Address Channel
  output  [3:0]     aruser_1_6;
  output  [3:0]     arid_1_6;
  output  [31:0]    araddr_1_6;
  output  [7:0]     arlen_1_6;
  output  [2:0]     arsize_1_6;
  output  [1:0]     arburst_1_6;
  output            arlock_1_6;
  output  [3:0]     arcache_1_6;
  output  [2:0]     arprot_1_6;
  output            arvalid_1_6;
  output            arvalid_vect_1_6;
  input             arready_1_6;
  output  [3:0]     ar_qv_1_6;

  // Read Channel
  input [3:0]       rid_1_6;
  input [31:0]      rdata_1_6;
  input [1:0]       rresp_1_6;
  input             rlast_1_6;
  input             rvalid_1_6;
  output            rready_1_6;

  // Connects SlaveInterface 1  to MasterInterface 8

  // Write Address Channel
  output [3:0]      awuser_1_8;
  output [3:0]      awid_1_8;
  output [31:0]     awaddr_1_8;
  output [7:0]      awlen_1_8;
  output [2:0]      awsize_1_8;
  output [1:0]      awburst_1_8;
  output            awlock_1_8;
  output [3:0]      awcache_1_8;
  output [2:0]      awprot_1_8;
  output            awvalid_1_8;
  output             awvalid_vect_1_8;
  input             awready_1_8;
  output [3:0]      aw_qv_1_8;
   
  // Write Channel
  output  [31:0]    wdata_1_8;
  output  [3:0]     wstrb_1_8;
  output            wlast_1_8;
  output            wvalid_1_8;
  input             wready_1_8;

  // Write Response Channel
  input [3:0]       bid_1_8;
  input [1:0]       bresp_1_8;
  input             bvalid_1_8;
  output            bready_1_8;

  // Read Address Channel
  output  [3:0]     aruser_1_8;
  output  [3:0]     arid_1_8;
  output  [31:0]    araddr_1_8;
  output  [7:0]     arlen_1_8;
  output  [2:0]     arsize_1_8;
  output  [1:0]     arburst_1_8;
  output            arlock_1_8;
  output  [3:0]     arcache_1_8;
  output  [2:0]     arprot_1_8;
  output            arvalid_1_8;
  output            arvalid_vect_1_8;
  input             arready_1_8;
  output  [3:0]     ar_qv_1_8;

  // Read Channel
  input [3:0]       rid_1_8;
  input [31:0]      rdata_1_8;
  input [1:0]       rresp_1_8;
  input             rlast_1_8;
  input             rvalid_1_8;
  output            rready_1_8;
 
  // Miscelaneous connections
  input             aclk;
  input             aresetn;

  // ---------------------------------------------------------------------------
  //  parameters
  // ---------------------------------------------------------------------------

  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------

  //------------------------------------------------------------------------------
  // Wires 
  //------------------------------------------------------------------------------

  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------

  // Instantiate multi-layer build layer modules, one per slave interface 
nic400_switch2_ml_blayer_0_ysyx_rv32 u_nic400_switch2_ml_blayer_0_ysyx_rv32
  (    
        // External AXI Connections 
        // SlaveInterface 0 (connects to Master axi_s_0)

        // Write Address Channel
        .awuser_s       (awuser_s0),
        .awid_s         (awid_s0),
        .awaddr_s       (awaddr_s0),
        .awlen_s        (awlen_s0),
        .awsize_s       (awsize_s0),
        .awburst_s      (awburst_s0),
        .awlock_s       (awlock_s0),
        .awcache_s      (awcache_s0),
        .awprot_s       (awprot_s0),
        .awvalid_s      (awvalid_s0),
        .awvalid_vect_s (awvalid_vect_s0),
        .awready_s      (awready_s0),
        .aw_qv_s        (aw_qv_s0),
   
        // Write Channel
        .wdata_s        (wdata_s0),
        .wstrb_s        (wstrb_s0),   
        .wlast_s        (wlast_s0),
        .wvalid_s       (wvalid_s0),
        .wready_s       (wready_s0),

        // Write Response Channel
        .bid_s          (bid_s0),
        .bresp_s        (bresp_s0),
        .bvalid_s       (bvalid_s0),
        .bready_s       (bready_s0),  

        // Read Address Channel
        .aruser_s       (aruser_s0),
        .arid_s         (arid_s0),
        .araddr_s       (araddr_s0),
        .arlen_s        (arlen_s0),
        .arsize_s       (arsize_s0),
        .arburst_s      (arburst_s0),
        .arlock_s       (arlock_s0),
        .arcache_s      (arcache_s0),
        .arprot_s       (arprot_s0),
        .arvalid_s      (arvalid_s0),
        .arvalid_vect_s (arvalid_vect_s0),
        .arready_s      (arready_s0),
        .ar_qv_s        (ar_qv_s0),
   
        // Read Channel
        .rid_s          (rid_s0),
        .rdata_s        (rdata_s0),
        .rresp_s        (rresp_s0),
        .rlast_s        (rlast_s0),
        .rvalid_s       (rvalid_s0),
        .rready_s       (rready_s0),

        // Internal AXI Connections 



        // Connects SlaveInterface 0  to Master Interface 0)

        // Write Address Channel
        .awuser_m0       (awuser_0_0),
        .awid_m0         (awid_0_0),
        .awaddr_m0       (awaddr_0_0),
        .awlen_m0        (awlen_0_0),
        .awsize_m0       (awsize_0_0),
        .awburst_m0      (awburst_0_0),
        .awlock_m0       (awlock_0_0),
        .awcache_m0      (awcache_0_0),
        .awprot_m0       (awprot_0_0),
        .awvalid_m0      (awvalid_0_0),
        .awvalid_vect_m0 (awvalid_vect_0_0),
        .awready_m0      (awready_0_0),
        .aw_qv_m0        (aw_qv_0_0),
   
        // Write Channel
        .wdata_m0        (wdata_0_0),
        .wstrb_m0        (wstrb_0_0),   
        .wlast_m0        (wlast_0_0),
        .wvalid_m0       (wvalid_0_0),
        .wready_m0       (wready_0_0),

        // Write Response Channel
        .bid_m0          (bid_0_0),
        .bresp_m0        (bresp_0_0),
        .bvalid_m0       (bvalid_0_0),
        .bready_m0       (bready_0_0),

        // Read Address Channel
        .aruser_m0       (aruser_0_0),
        .arid_m0         (arid_0_0),
        .araddr_m0       (araddr_0_0),
        .arlen_m0        (arlen_0_0),
        .arsize_m0       (arsize_0_0),
        .arburst_m0      (arburst_0_0),
        .arlock_m0       (arlock_0_0),
        .arcache_m0      (arcache_0_0),
        .arprot_m0       (arprot_0_0),
        .arvalid_m0      (arvalid_0_0),
        .arvalid_vect_m0 (arvalid_vect_0_0),
        .arready_m0      (arready_0_0),
        .ar_qv_m0        (ar_qv_0_0),
   
        // Read Channel
        .rid_m0          (rid_0_0),
        .rdata_m0        (rdata_0_0),
        .rresp_m0        (rresp_0_0),
        .rlast_m0        (rlast_0_0),
        .rvalid_m0       (rvalid_0_0),
        .rready_m0       (rready_0_0),

        // Connects SlaveInterface 0  to Master Interface 1)

        // Write Address Channel
        .awuser_m1       (awuser_0_1),
        .awid_m1         (awid_0_1),
        .awaddr_m1       (awaddr_0_1),
        .awlen_m1        (awlen_0_1),
        .awsize_m1       (awsize_0_1),
        .awburst_m1      (awburst_0_1),
        .awlock_m1       (awlock_0_1),
        .awcache_m1      (awcache_0_1),
        .awprot_m1       (awprot_0_1),
        .awvalid_m1      (awvalid_0_1),
        .awvalid_vect_m1 (awvalid_vect_0_1),
        .awready_m1      (awready_0_1),
        .aw_qv_m1        (aw_qv_0_1),
   
        // Write Channel
        .wdata_m1        (wdata_0_1),
        .wstrb_m1        (wstrb_0_1),   
        .wlast_m1        (wlast_0_1),
        .wvalid_m1       (wvalid_0_1),
        .wready_m1       (wready_0_1),

        // Write Response Channel
        .bid_m1          (bid_0_1),
        .bresp_m1        (bresp_0_1),
        .bvalid_m1       (bvalid_0_1),
        .bready_m1       (bready_0_1),

        // Read Address Channel
        .aruser_m1       (aruser_0_1),
        .arid_m1         (arid_0_1),
        .araddr_m1       (araddr_0_1),
        .arlen_m1        (arlen_0_1),
        .arsize_m1       (arsize_0_1),
        .arburst_m1      (arburst_0_1),
        .arlock_m1       (arlock_0_1),
        .arcache_m1      (arcache_0_1),
        .arprot_m1       (arprot_0_1),
        .arvalid_m1      (arvalid_0_1),
        .arvalid_vect_m1 (arvalid_vect_0_1),
        .arready_m1      (arready_0_1),
        .ar_qv_m1        (ar_qv_0_1),
   
        // Read Channel
        .rid_m1          (rid_0_1),
        .rdata_m1        (rdata_0_1),
        .rresp_m1        (rresp_0_1),
        .rlast_m1        (rlast_0_1),
        .rvalid_m1       (rvalid_0_1),
        .rready_m1       (rready_0_1),

        // Connects SlaveInterface 0  to Master Interface 2)

        // Write Address Channel
        .awuser_m2       (awuser_0_2),
        .awid_m2         (awid_0_2),
        .awaddr_m2       (awaddr_0_2),
        .awlen_m2        (awlen_0_2),
        .awsize_m2       (awsize_0_2),
        .awburst_m2      (awburst_0_2),
        .awlock_m2       (awlock_0_2),
        .awcache_m2      (awcache_0_2),
        .awprot_m2       (awprot_0_2),
        .awvalid_m2      (awvalid_0_2),
        .awvalid_vect_m2 (awvalid_vect_0_2),
        .awready_m2      (awready_0_2),
        .aw_qv_m2        (aw_qv_0_2),
   
        // Write Channel
        .wdata_m2        (wdata_0_2),
        .wstrb_m2        (wstrb_0_2),   
        .wlast_m2        (wlast_0_2),
        .wvalid_m2       (wvalid_0_2),
        .wready_m2       (wready_0_2),

        // Write Response Channel
        .bid_m2          (bid_0_2),
        .bresp_m2        (bresp_0_2),
        .bvalid_m2       (bvalid_0_2),
        .bready_m2       (bready_0_2),

        // Read Address Channel
        .aruser_m2       (aruser_0_2),
        .arid_m2         (arid_0_2),
        .araddr_m2       (araddr_0_2),
        .arlen_m2        (arlen_0_2),
        .arsize_m2       (arsize_0_2),
        .arburst_m2      (arburst_0_2),
        .arlock_m2       (arlock_0_2),
        .arcache_m2      (arcache_0_2),
        .arprot_m2       (arprot_0_2),
        .arvalid_m2      (arvalid_0_2),
        .arvalid_vect_m2 (arvalid_vect_0_2),
        .arready_m2      (arready_0_2),
        .ar_qv_m2        (ar_qv_0_2),
   
        // Read Channel
        .rid_m2          (rid_0_2),
        .rdata_m2        (rdata_0_2),
        .rresp_m2        (rresp_0_2),
        .rlast_m2        (rlast_0_2),
        .rvalid_m2       (rvalid_0_2),
        .rready_m2       (rready_0_2),

        // Connects SlaveInterface 0  to Master Interface 3)

        // Write Address Channel
        .awuser_m3       (awuser_0_3),
        .awid_m3         (awid_0_3),
        .awaddr_m3       (awaddr_0_3),
        .awlen_m3        (awlen_0_3),
        .awsize_m3       (awsize_0_3),
        .awburst_m3      (awburst_0_3),
        .awlock_m3       (awlock_0_3),
        .awcache_m3      (awcache_0_3),
        .awprot_m3       (awprot_0_3),
        .awvalid_m3      (awvalid_0_3),
        .awvalid_vect_m3 (awvalid_vect_0_3),
        .awready_m3      (awready_0_3),
        .aw_qv_m3        (aw_qv_0_3),
   
        // Write Channel
        .wdata_m3        (wdata_0_3),
        .wstrb_m3        (wstrb_0_3),   
        .wlast_m3        (wlast_0_3),
        .wvalid_m3       (wvalid_0_3),
        .wready_m3       (wready_0_3),

        // Write Response Channel
        .bid_m3          (bid_0_3),
        .bresp_m3        (bresp_0_3),
        .bvalid_m3       (bvalid_0_3),
        .bready_m3       (bready_0_3),

        // Read Address Channel
        .aruser_m3       (aruser_0_3),
        .arid_m3         (arid_0_3),
        .araddr_m3       (araddr_0_3),
        .arlen_m3        (arlen_0_3),
        .arsize_m3       (arsize_0_3),
        .arburst_m3      (arburst_0_3),
        .arlock_m3       (arlock_0_3),
        .arcache_m3      (arcache_0_3),
        .arprot_m3       (arprot_0_3),
        .arvalid_m3      (arvalid_0_3),
        .arvalid_vect_m3 (arvalid_vect_0_3),
        .arready_m3      (arready_0_3),
        .ar_qv_m3        (ar_qv_0_3),
   
        // Read Channel
        .rid_m3          (rid_0_3),
        .rdata_m3        (rdata_0_3),
        .rresp_m3        (rresp_0_3),
        .rlast_m3        (rlast_0_3),
        .rvalid_m3       (rvalid_0_3),
        .rready_m3       (rready_0_3),

        // Connects SlaveInterface 0  to Master Interface 4)

        // Write Address Channel
        .awuser_m4       (awuser_0_4),
        .awid_m4         (awid_0_4),
        .awaddr_m4       (awaddr_0_4),
        .awlen_m4        (awlen_0_4),
        .awsize_m4       (awsize_0_4),
        .awburst_m4      (awburst_0_4),
        .awlock_m4       (awlock_0_4),
        .awcache_m4      (awcache_0_4),
        .awprot_m4       (awprot_0_4),
        .awvalid_m4      (awvalid_0_4),
        .awvalid_vect_m4 (awvalid_vect_0_4),
        .awready_m4      (awready_0_4),
        .aw_qv_m4        (aw_qv_0_4),
   
        // Write Channel
        .wdata_m4        (wdata_0_4),
        .wstrb_m4        (wstrb_0_4),   
        .wlast_m4        (wlast_0_4),
        .wvalid_m4       (wvalid_0_4),
        .wready_m4       (wready_0_4),

        // Write Response Channel
        .bid_m4          (bid_0_4),
        .bresp_m4        (bresp_0_4),
        .bvalid_m4       (bvalid_0_4),
        .bready_m4       (bready_0_4),

        // Read Address Channel
        .aruser_m4       (aruser_0_4),
        .arid_m4         (arid_0_4),
        .araddr_m4       (araddr_0_4),
        .arlen_m4        (arlen_0_4),
        .arsize_m4       (arsize_0_4),
        .arburst_m4      (arburst_0_4),
        .arlock_m4       (arlock_0_4),
        .arcache_m4      (arcache_0_4),
        .arprot_m4       (arprot_0_4),
        .arvalid_m4      (arvalid_0_4),
        .arvalid_vect_m4 (arvalid_vect_0_4),
        .arready_m4      (arready_0_4),
        .ar_qv_m4        (ar_qv_0_4),
   
        // Read Channel
        .rid_m4          (rid_0_4),
        .rdata_m4        (rdata_0_4),
        .rresp_m4        (rresp_0_4),
        .rlast_m4        (rlast_0_4),
        .rvalid_m4       (rvalid_0_4),
        .rready_m4       (rready_0_4),

        // Connects SlaveInterface 0  to Master Interface 5)

        // Write Address Channel
        .awuser_m5       (awuser_0_5),
        .awid_m5         (awid_0_5),
        .awaddr_m5       (awaddr_0_5),
        .awlen_m5        (awlen_0_5),
        .awsize_m5       (awsize_0_5),
        .awburst_m5      (awburst_0_5),
        .awlock_m5       (awlock_0_5),
        .awcache_m5      (awcache_0_5),
        .awprot_m5       (awprot_0_5),
        .awvalid_m5      (awvalid_0_5),
        .awvalid_vect_m5 (awvalid_vect_0_5),
        .awready_m5      (awready_0_5),
        .aw_qv_m5        (aw_qv_0_5),
   
        // Write Channel
        .wdata_m5        (wdata_0_5),
        .wstrb_m5        (wstrb_0_5),   
        .wlast_m5        (wlast_0_5),
        .wvalid_m5       (wvalid_0_5),
        .wready_m5       (wready_0_5),

        // Write Response Channel
        .bid_m5          (bid_0_5),
        .bresp_m5        (bresp_0_5),
        .bvalid_m5       (bvalid_0_5),
        .bready_m5       (bready_0_5),

        // Read Address Channel
        .aruser_m5       (aruser_0_5),
        .arid_m5         (arid_0_5),
        .araddr_m5       (araddr_0_5),
        .arlen_m5        (arlen_0_5),
        .arsize_m5       (arsize_0_5),
        .arburst_m5      (arburst_0_5),
        .arlock_m5       (arlock_0_5),
        .arcache_m5      (arcache_0_5),
        .arprot_m5       (arprot_0_5),
        .arvalid_m5      (arvalid_0_5),
        .arvalid_vect_m5 (arvalid_vect_0_5),
        .arready_m5      (arready_0_5),
        .ar_qv_m5        (ar_qv_0_5),
   
        // Read Channel
        .rid_m5          (rid_0_5),
        .rdata_m5        (rdata_0_5),
        .rresp_m5        (rresp_0_5),
        .rlast_m5        (rlast_0_5),
        .rvalid_m5       (rvalid_0_5),
        .rready_m5       (rready_0_5),

        // Connects SlaveInterface 0  to Master Interface 6)

        // Write Address Channel
        .awuser_m6       (awuser_0_6),
        .awid_m6         (awid_0_6),
        .awaddr_m6       (awaddr_0_6),
        .awlen_m6        (awlen_0_6),
        .awsize_m6       (awsize_0_6),
        .awburst_m6      (awburst_0_6),
        .awlock_m6       (awlock_0_6),
        .awcache_m6      (awcache_0_6),
        .awprot_m6       (awprot_0_6),
        .awvalid_m6      (awvalid_0_6),
        .awvalid_vect_m6 (awvalid_vect_0_6),
        .awready_m6      (awready_0_6),
        .aw_qv_m6        (aw_qv_0_6),
   
        // Write Channel
        .wdata_m6        (wdata_0_6),
        .wstrb_m6        (wstrb_0_6),   
        .wlast_m6        (wlast_0_6),
        .wvalid_m6       (wvalid_0_6),
        .wready_m6       (wready_0_6),

        // Write Response Channel
        .bid_m6          (bid_0_6),
        .bresp_m6        (bresp_0_6),
        .bvalid_m6       (bvalid_0_6),
        .bready_m6       (bready_0_6),

        // Read Address Channel
        .aruser_m6       (aruser_0_6),
        .arid_m6         (arid_0_6),
        .araddr_m6       (araddr_0_6),
        .arlen_m6        (arlen_0_6),
        .arsize_m6       (arsize_0_6),
        .arburst_m6      (arburst_0_6),
        .arlock_m6       (arlock_0_6),
        .arcache_m6      (arcache_0_6),
        .arprot_m6       (arprot_0_6),
        .arvalid_m6      (arvalid_0_6),
        .arvalid_vect_m6 (arvalid_vect_0_6),
        .arready_m6      (arready_0_6),
        .ar_qv_m6        (ar_qv_0_6),
   
        // Read Channel
        .rid_m6          (rid_0_6),
        .rdata_m6        (rdata_0_6),
        .rresp_m6        (rresp_0_6),
        .rlast_m6        (rlast_0_6),
        .rvalid_m6       (rvalid_0_6),
        .rready_m6       (rready_0_6),

        // Connects SlaveInterface 0  to Master Interface 7)

        // Write Address Channel
        .awuser_m7       (awuser_0_7),
        .awid_m7         (awid_0_7),
        .awaddr_m7       (awaddr_0_7),
        .awlen_m7        (awlen_0_7),
        .awsize_m7       (awsize_0_7),
        .awburst_m7      (awburst_0_7),
        .awlock_m7       (awlock_0_7),
        .awcache_m7      (awcache_0_7),
        .awprot_m7       (awprot_0_7),
        .awvalid_m7      (awvalid_0_7),
        .awvalid_vect_m7 (awvalid_vect_0_7),
        .awready_m7      (awready_0_7),
        .aw_qv_m7        (aw_qv_0_7),
   
        // Write Channel
        .wdata_m7        (wdata_0_7),
        .wstrb_m7        (wstrb_0_7),   
        .wlast_m7        (wlast_0_7),
        .wvalid_m7       (wvalid_0_7),
        .wready_m7       (wready_0_7),

        // Write Response Channel
        .bid_m7          (bid_0_7),
        .bresp_m7        (bresp_0_7),
        .bvalid_m7       (bvalid_0_7),
        .bready_m7       (bready_0_7),

        // Read Address Channel
        .aruser_m7       (aruser_0_7),
        .arid_m7         (arid_0_7),
        .araddr_m7       (araddr_0_7),
        .arlen_m7        (arlen_0_7),
        .arsize_m7       (arsize_0_7),
        .arburst_m7      (arburst_0_7),
        .arlock_m7       (arlock_0_7),
        .arcache_m7      (arcache_0_7),
        .arprot_m7       (arprot_0_7),
        .arvalid_m7      (arvalid_0_7),
        .arvalid_vect_m7 (arvalid_vect_0_7),
        .arready_m7      (arready_0_7),
        .ar_qv_m7        (ar_qv_0_7),
   
        // Read Channel
        .rid_m7          (rid_0_7),
        .rdata_m7        (rdata_0_7),
        .rresp_m7        (rresp_0_7),
        .rlast_m7        (rlast_0_7),
        .rvalid_m7       (rvalid_0_7),
        .rready_m7       (rready_0_7),

        // Connects SlaveInterface 0  to Master Interface 8)

        // Write Address Channel
        .awuser_m8       (awuser_0_8),
        .awid_m8         (awid_0_8),
        .awaddr_m8       (awaddr_0_8),
        .awlen_m8        (awlen_0_8),
        .awsize_m8       (awsize_0_8),
        .awburst_m8      (awburst_0_8),
        .awlock_m8       (awlock_0_8),
        .awcache_m8      (awcache_0_8),
        .awprot_m8       (awprot_0_8),
        .awvalid_m8      (awvalid_0_8),
        .awvalid_vect_m8 (awvalid_vect_0_8),
        .awready_m8      (awready_0_8),
        .aw_qv_m8        (aw_qv_0_8),
   
        // Write Channel
        .wdata_m8        (wdata_0_8),
        .wstrb_m8        (wstrb_0_8),   
        .wlast_m8        (wlast_0_8),
        .wvalid_m8       (wvalid_0_8),
        .wready_m8       (wready_0_8),

        // Write Response Channel
        .bid_m8          (bid_0_8),
        .bresp_m8        (bresp_0_8),
        .bvalid_m8       (bvalid_0_8),
        .bready_m8       (bready_0_8),

        // Read Address Channel
        .aruser_m8       (aruser_0_8),
        .arid_m8         (arid_0_8),
        .araddr_m8       (araddr_0_8),
        .arlen_m8        (arlen_0_8),
        .arsize_m8       (arsize_0_8),
        .arburst_m8      (arburst_0_8),
        .arlock_m8       (arlock_0_8),
        .arcache_m8      (arcache_0_8),
        .arprot_m8       (arprot_0_8),
        .arvalid_m8      (arvalid_0_8),
        .arvalid_vect_m8 (arvalid_vect_0_8),
        .arready_m8      (arready_0_8),
        .ar_qv_m8        (ar_qv_0_8),
   
        // Read Channel
        .rid_m8          (rid_0_8),
        .rdata_m8        (rdata_0_8),
        .rresp_m8        (rresp_0_8),
        .rlast_m8        (rlast_0_8),
        .rvalid_m8       (rvalid_0_8),
        .rready_m8       (rready_0_8),
        // Miscelaneous connections
        .aclk    (aclk),
        .aresetn    (aresetn)
  ); 

nic400_switch2_ml_blayer_1_ysyx_rv32 u_nic400_switch2_ml_blayer_1_ysyx_rv32
  (    
        // External AXI Connections 
        // SlaveInterface 1 (connects to Master axi_s_1)

        // Write Address Channel
        .awuser_s       (awuser_s1),
        .awid_s         (awid_s1),
        .awaddr_s       (awaddr_s1),
        .awlen_s        (awlen_s1),
        .awsize_s       (awsize_s1),
        .awburst_s      (awburst_s1),
        .awlock_s       (awlock_s1),
        .awcache_s      (awcache_s1),
        .awprot_s       (awprot_s1),
        .awvalid_s      (awvalid_s1),
        .awvalid_vect_s (awvalid_vect_s1),
        .awready_s      (awready_s1),
        .aw_qv_s        (aw_qv_s1),
   
        // Write Channel
        .wdata_s        (wdata_s1),
        .wstrb_s        (wstrb_s1),   
        .wlast_s        (wlast_s1),
        .wvalid_s       (wvalid_s1),
        .wready_s       (wready_s1),

        // Write Response Channel
        .bid_s          (bid_s1),
        .bresp_s        (bresp_s1),
        .bvalid_s       (bvalid_s1),
        .bready_s       (bready_s1),  

        // Read Address Channel
        .aruser_s       (aruser_s1),
        .arid_s         (arid_s1),
        .araddr_s       (araddr_s1),
        .arlen_s        (arlen_s1),
        .arsize_s       (arsize_s1),
        .arburst_s      (arburst_s1),
        .arlock_s       (arlock_s1),
        .arcache_s      (arcache_s1),
        .arprot_s       (arprot_s1),
        .arvalid_s      (arvalid_s1),
        .arvalid_vect_s (arvalid_vect_s1),
        .arready_s      (arready_s1),
        .ar_qv_s        (ar_qv_s1),
   
        // Read Channel
        .rid_s          (rid_s1),
        .rdata_s        (rdata_s1),
        .rresp_s        (rresp_s1),
        .rlast_s        (rlast_s1),
        .rvalid_s       (rvalid_s1),
        .rready_s       (rready_s1),

        // Internal AXI Connections 



        // Connects SlaveInterface 1  to Master Interface 2)

        // Write Address Channel
        .awuser_m0       (awuser_1_2),
        .awid_m0         (awid_1_2),
        .awaddr_m0       (awaddr_1_2),
        .awlen_m0        (awlen_1_2),
        .awsize_m0       (awsize_1_2),
        .awburst_m0      (awburst_1_2),
        .awlock_m0       (awlock_1_2),
        .awcache_m0      (awcache_1_2),
        .awprot_m0       (awprot_1_2),
        .awvalid_m0      (awvalid_1_2),
        .awvalid_vect_m0 (awvalid_vect_1_2),
        .awready_m0      (awready_1_2),
        .aw_qv_m0        (aw_qv_1_2),
   
        // Write Channel
        .wdata_m0        (wdata_1_2),
        .wstrb_m0        (wstrb_1_2),   
        .wlast_m0        (wlast_1_2),
        .wvalid_m0       (wvalid_1_2),
        .wready_m0       (wready_1_2),

        // Write Response Channel
        .bid_m0          (bid_1_2),
        .bresp_m0        (bresp_1_2),
        .bvalid_m0       (bvalid_1_2),
        .bready_m0       (bready_1_2),

        // Read Address Channel
        .aruser_m0       (aruser_1_2),
        .arid_m0         (arid_1_2),
        .araddr_m0       (araddr_1_2),
        .arlen_m0        (arlen_1_2),
        .arsize_m0       (arsize_1_2),
        .arburst_m0      (arburst_1_2),
        .arlock_m0       (arlock_1_2),
        .arcache_m0      (arcache_1_2),
        .arprot_m0       (arprot_1_2),
        .arvalid_m0      (arvalid_1_2),
        .arvalid_vect_m0 (arvalid_vect_1_2),
        .arready_m0      (arready_1_2),
        .ar_qv_m0        (ar_qv_1_2),
   
        // Read Channel
        .rid_m0          (rid_1_2),
        .rdata_m0        (rdata_1_2),
        .rresp_m0        (rresp_1_2),
        .rlast_m0        (rlast_1_2),
        .rvalid_m0       (rvalid_1_2),
        .rready_m0       (rready_1_2),

        // Connects SlaveInterface 1  to Master Interface 3)

        // Write Address Channel
        .awuser_m1       (awuser_1_3),
        .awid_m1         (awid_1_3),
        .awaddr_m1       (awaddr_1_3),
        .awlen_m1        (awlen_1_3),
        .awsize_m1       (awsize_1_3),
        .awburst_m1      (awburst_1_3),
        .awlock_m1       (awlock_1_3),
        .awcache_m1      (awcache_1_3),
        .awprot_m1       (awprot_1_3),
        .awvalid_m1      (awvalid_1_3),
        .awvalid_vect_m1 (awvalid_vect_1_3),
        .awready_m1      (awready_1_3),
        .aw_qv_m1        (aw_qv_1_3),
   
        // Write Channel
        .wdata_m1        (wdata_1_3),
        .wstrb_m1        (wstrb_1_3),   
        .wlast_m1        (wlast_1_3),
        .wvalid_m1       (wvalid_1_3),
        .wready_m1       (wready_1_3),

        // Write Response Channel
        .bid_m1          (bid_1_3),
        .bresp_m1        (bresp_1_3),
        .bvalid_m1       (bvalid_1_3),
        .bready_m1       (bready_1_3),

        // Read Address Channel
        .aruser_m1       (aruser_1_3),
        .arid_m1         (arid_1_3),
        .araddr_m1       (araddr_1_3),
        .arlen_m1        (arlen_1_3),
        .arsize_m1       (arsize_1_3),
        .arburst_m1      (arburst_1_3),
        .arlock_m1       (arlock_1_3),
        .arcache_m1      (arcache_1_3),
        .arprot_m1       (arprot_1_3),
        .arvalid_m1      (arvalid_1_3),
        .arvalid_vect_m1 (arvalid_vect_1_3),
        .arready_m1      (arready_1_3),
        .ar_qv_m1        (ar_qv_1_3),
   
        // Read Channel
        .rid_m1          (rid_1_3),
        .rdata_m1        (rdata_1_3),
        .rresp_m1        (rresp_1_3),
        .rlast_m1        (rlast_1_3),
        .rvalid_m1       (rvalid_1_3),
        .rready_m1       (rready_1_3),

        // Connects SlaveInterface 1  to Master Interface 6)

        // Write Address Channel
        .awuser_m2       (awuser_1_6),
        .awid_m2         (awid_1_6),
        .awaddr_m2       (awaddr_1_6),
        .awlen_m2        (awlen_1_6),
        .awsize_m2       (awsize_1_6),
        .awburst_m2      (awburst_1_6),
        .awlock_m2       (awlock_1_6),
        .awcache_m2      (awcache_1_6),
        .awprot_m2       (awprot_1_6),
        .awvalid_m2      (awvalid_1_6),
        .awvalid_vect_m2 (awvalid_vect_1_6),
        .awready_m2      (awready_1_6),
        .aw_qv_m2        (aw_qv_1_6),
   
        // Write Channel
        .wdata_m2        (wdata_1_6),
        .wstrb_m2        (wstrb_1_6),   
        .wlast_m2        (wlast_1_6),
        .wvalid_m2       (wvalid_1_6),
        .wready_m2       (wready_1_6),

        // Write Response Channel
        .bid_m2          (bid_1_6),
        .bresp_m2        (bresp_1_6),
        .bvalid_m2       (bvalid_1_6),
        .bready_m2       (bready_1_6),

        // Read Address Channel
        .aruser_m2       (aruser_1_6),
        .arid_m2         (arid_1_6),
        .araddr_m2       (araddr_1_6),
        .arlen_m2        (arlen_1_6),
        .arsize_m2       (arsize_1_6),
        .arburst_m2      (arburst_1_6),
        .arlock_m2       (arlock_1_6),
        .arcache_m2      (arcache_1_6),
        .arprot_m2       (arprot_1_6),
        .arvalid_m2      (arvalid_1_6),
        .arvalid_vect_m2 (arvalid_vect_1_6),
        .arready_m2      (arready_1_6),
        .ar_qv_m2        (ar_qv_1_6),
   
        // Read Channel
        .rid_m2          (rid_1_6),
        .rdata_m2        (rdata_1_6),
        .rresp_m2        (rresp_1_6),
        .rlast_m2        (rlast_1_6),
        .rvalid_m2       (rvalid_1_6),
        .rready_m2       (rready_1_6),

        // Connects SlaveInterface 1  to Master Interface 8)

        // Write Address Channel
        .awuser_m3       (awuser_1_8),
        .awid_m3         (awid_1_8),
        .awaddr_m3       (awaddr_1_8),
        .awlen_m3        (awlen_1_8),
        .awsize_m3       (awsize_1_8),
        .awburst_m3      (awburst_1_8),
        .awlock_m3       (awlock_1_8),
        .awcache_m3      (awcache_1_8),
        .awprot_m3       (awprot_1_8),
        .awvalid_m3      (awvalid_1_8),
        .awvalid_vect_m3 (awvalid_vect_1_8),
        .awready_m3      (awready_1_8),
        .aw_qv_m3        (aw_qv_1_8),
   
        // Write Channel
        .wdata_m3        (wdata_1_8),
        .wstrb_m3        (wstrb_1_8),   
        .wlast_m3        (wlast_1_8),
        .wvalid_m3       (wvalid_1_8),
        .wready_m3       (wready_1_8),

        // Write Response Channel
        .bid_m3          (bid_1_8),
        .bresp_m3        (bresp_1_8),
        .bvalid_m3       (bvalid_1_8),
        .bready_m3       (bready_1_8),

        // Read Address Channel
        .aruser_m3       (aruser_1_8),
        .arid_m3         (arid_1_8),
        .araddr_m3       (araddr_1_8),
        .arlen_m3        (arlen_1_8),
        .arsize_m3       (arsize_1_8),
        .arburst_m3      (arburst_1_8),
        .arlock_m3       (arlock_1_8),
        .arcache_m3      (arcache_1_8),
        .arprot_m3       (arprot_1_8),
        .arvalid_m3      (arvalid_1_8),
        .arvalid_vect_m3 (arvalid_vect_1_8),
        .arready_m3      (arready_1_8),
        .ar_qv_m3        (ar_qv_1_8),
   
        // Read Channel
        .rid_m3          (rid_1_8),
        .rdata_m3        (rdata_1_8),
        .rresp_m3        (rresp_1_8),
        .rlast_m3        (rlast_1_8),
        .rvalid_m3       (rvalid_1_8),
        .rready_m3       (rready_1_8),
        // Miscelaneous connections
        .aclk    (aclk),
        .aresetn    (aresetn)
  ); 





  endmodule

//  --=============================== End ====================================--

